The present invention relates to the field of testing integrated circuits. More particularly, the present invention relates to testing integrated circuits under high-temperature conditions.
Integrated circuits are often tested after manufacture by electrically stressing the devices in an elevated temperature for a period of time to cause failure of marginal devices. This process is referred to as burn-in. Multiple integrated circuit chips are placed on a burn-in board that is similar to a computer add-on card, but usually much larger. The burn-in board is a printed circuit board with receptacles for the integrated circuit chips. The burn-in board also includes printed circuit connections between pins of the integrated circuit chips and connectors of the burn-in board.
FIG. 1 shows a prior integrated circuit testing system 100. Oven 202 encloses multiple burn-in boards, each of which holds multiple integrated circuit (xe2x80x9cICxe2x80x9d) chips. The burn-in boards (not visible in FIG. 1) inside oven 202 are electrically connected to respective driver/interface boards 211a through 211n, 212a through 212n, and 213a through 213n. Each driver/interface board of driver/interface boards 211a through 211n, 212a through 212n, and 213a through 213n is electrically connected in turn to computer 206. Computer 206 controls the driver/interface boards with software that controls the testing of the integrated circuit chips.
FIG. 2 is a cutaway transparent view of oven 202 showing one row of burn-in boards 208a through 208n secured in one rack 210 within oven 202. For example, seventy-two burn-in boards can be placed in oven 202 at one time through the use of multiple racks at various levels. Other numbers of burn-in boards are possible.
Burn-in boards 208a through 208n have respective male connectors 204a through 204n. Typically, each burn-in board of boards 208a through 208n has seventy-two electrical strip contacts that comprise the male connector. For example, connector 204a has seventy-two contacts, with thirty-six of the contacts on one side of connector 204a and thirty-six of the contacts on the opposite side of connector 204a. 
Driver/interface boards 211a through 211n have respective female connectors 205a through 205n. Typically, each driver/interface board of boards 211a through 211n has seventy-two contacts that comprise the female connector. For example, connector 205a has seventy-two contacts, with thirty-six of the contacts on one side of connector 205a and thirty-six of the contacts on the opposite side of connector 205a. 
Male connectors 204a through 204n are connected into respective female connectors 205a through 205n and provide electrical pathways between driver/interface boards 211a through 211n and burn-in boards 208a through 208n. Driver/interface boards 211a through 211n are in turn electrically connected to computer 206. Burn-in boards 208a through 208neach include IC chips 302a-n through 312a-n, and those IC chips are accordingly electrically connected to computer 206.
As shown in FIG. 2, multiple integrated circuit chips 302a through 302n are arranged in columns and rows on burn-in board 208a. Each of integrated circuit chips 302a through 302n receives clock, power, and ground signals. Each of integrated circuit chips 302a through 302n is powered during the entire test period. Some of the contacts of connectors 204a and 205a are used for clock, power, and ground signals. This reduces the number of contacts available to carry other signals. For example, typically eight contacts are used on connector 204a to carry clock, power, and ground signals, leaving sixty-four contacts available to carry other signals. The other burn-in boards 208b through 208n have similar configurations. For example, integrated circuit chips 303a through 303n reside on burn-in board 208b, and integrated circuit chips 312a through 312n reside on burn-in board 208n. 
For a burn-in board such as burn-in board 208a, the number of IC chips 302a through 302n is limited by the number of contacts of connector 204a and by the number of pins being used on each of the IC chips 302a through 302n under test. Different types of IC chips have different pin-outs.
For instance, an IC chip with sixteen pins and two control signals typically requires fewer signals at any one time than an IC chip with forty-eight pins and four control signals. An IC chip requiring fewer signals at any one time during the burn-in procedure requires the use of fewer contacts of connector 204a at any one time. It follows that burn-in board 208a can accommodate more of those IC chips that require few signals than those IC chips that require many signals. For a memory having a 32-bit data word and 215 (i.e., 32k) address locations, seventy-two of these IC chips can be accommodated on burn-in board 208a. Similarly, seventy-two of these IC chips can be accommodated on each of burn-in boards 208b through 208n. 
Driver/interface board 211a includes driver area 304a and logic area 306a. Driver area 304a contains a driver for each contact within connector 205a on the driver/interface board. Logic area 306a contains logic for receiving and processing signals sent from computer 206 to burn-in board 208a. Driver/interface boards 311b through 311n have similar respective driver areas 304b though 304n and logic areas 306b through 306n. 
Typically in prior burn-in test systems a computer program causes computer 206 to send signals to the integrated circuit chips 302a-n through 312a-n on respective burn-in boards 208a through 208n via respective driver/interface boards 211a through 211n. The signals toggle various device pins under elevated temperatures for some test period. For example, pins of the IC chips 302a through 302n are sent alternating logic one and logic zero signalsxe2x80x94usually 5 volts alternating with zero volts. After some period, typically as long as twenty-four hours, the burn-in board 208a is removed from the oven. The integrated circuit chips 302a through 302n are then removed from the board 208a by hand and placed on an IC electrical tester (not shown) that resides outside of oven 202. The IC electrical tester is a separate external unit designed specifically for determining the functionality of the integrated circuit chips and operates the IC chips at room temperature. If any of the integrated circuit chips 302a through 302n failed during the burn-in process, the failure is discovered typically during various tests after burn-in, and each failed IC chip is discarded. A similar procedure is used for IC chips 303a-n through 312a-n of respective burn-in boards 208b through 208n. 
One disadvantage of the prior burn-in test system 100 is the need for extensive testing of IC chips after burn-in to determine whether they have failed. The external testers used for this testing are very expensive, usually costing millions of dollars, and are also expensive to operate. In addition, each test which must be performed by the external testers after burn-in requires more labor and time. For these reasons, it would be very desirable to perform functional tests on IC chips while they are undergoing burn-in.
Because of limitations of prior burn-in test systems, it is not possible to perform many functional tests on IC chips while they are in the oven. For example, for IC chips that are memory devices with data words of thirty-two bits or more, the typical burn-in board and driver/interface board pin configuration of prior burn-in test systems prevents the testing of the memory devices while they are in the oven 202. Because a limited number of pins 204a connect burn-in board 208a with the driver/interface board 211a, not enough pins 204a are available to carry various control signals and address signals at the same time as thirty-two data signals. This can be explained using, for example, a memory with 32-bit wide data words and a 215 (i.e., 32k) address space. Such a memory is typically referred to as a xe2x80x9c32Kxc3x9732xe2x80x9d memory. Fifteen address lines are needed to address the 215 address space. Assuming that there is an array of 8 rows and 9 columns of memories under test on a burn-in board, seventeen device select lines are required. Five lines are typically required for control and clock, but the number can vary depending on the particular memory under test. Fifteen address lines plus seventeen device select lines plus five control and clock lines results in a total of thirty-seven lines of that are used out of sixty-four available contacts of connector 204a. Thus, only twenty-seven contacts remain unused, which is not enough to carry thirty-two bits of data to be read from a memory device.
One object of the present invention is to provide a method and apparatus for testing integrated circuits during high-temperature stress testing such as during burn-in.
Another object of the present invention is to reduce the number of tests to be performed using expensive testing equipment after burn-in.
Another object is to allow increased test functionality in a test system with the use of standard burn-in boards and standard driver/interfaces.
An apparatus for testing an integrated circuit in an oven during burn-in is described. A burn-in board in the oven is electrically connected to a plurality of integrated circuit (xe2x80x9cICxe2x80x9d) components. A driver/interface board outside the oven is electrically connected to the burn-in board through a plurality of contacts and sends and receives a plurality of signals between the IC components and a test controller. A switch module on the burn-in board comprises a plurality of high-temperature switches for transferring signals between the plurality of IC components and the driver/interface board during burn-in. A plurality of signals entering the switch module from the driver/interface board does not exceed in number the plurality of contacts, and is fewer in number than a plurality of signals exiting the switch module to the plurality of IC components.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.